Semiconductor integrated circuits (IC) are manufactured using complex and time consuming processes to fabricate a wafer having large numbers of individual IC “chips”. Before the wafer is cut in order to test and package each of the chips, itself a laborious task, it is desirable to perform tests on the wafer as a whole. These tests are referred to as “full wafer” tests or probes.
A full wafer test is performed by aligning a probe card device having contacts that are positioned and aligned to make contact with corresponding bond pads on the wafer. Then, the probe card device supplies test signals through appropriate ones of the contacts to the bond pads on the wafer.
With increasing miniaturization of the chips on a wafer, more chips are formed on a single wafer, and the probe card to test these wafers must have more probe contacts in order to achieve full wafer contact. This results in a significant increase in the cost and complexity of probe cards. For example, if a wafer has 750 chips on it and each chip has 45 contact points, approximately 33,750 probe contacts would be required in order to establish full wafer contact. This presents a space problem on the probe card and increases the resulting force required for application to the wafer in order to achieve sufficient electrical contact at all of the probe contacts.
Solutions to this problem heretofore known involve providing more contact points on the probe card device or using multiple “touch downs” of the probe card device to the wafer. There is, therefore, room for improving the cost and time duration of the full wafer probe process.